Constant USDHC1_FREQUENCY 

pub const USDHC1_FREQUENCY: u32 = _; // 198_000_000u32

USDHC1 root clock frequency (Hz).

Derived from PLL2_PFD2 (396 MHz) divided by USDHC1_CLK_DIVISOR. The actual SD bus clock is further divided by the USDHC1 peripheral’s internal SDCLKFS and DVS dividers during card initialization.