Struct Resources

#[non_exhaustive]
pub struct Resources<Pins> {

    pub pit: Channels,
    pub gpt1: Gpt1,
    pub gpt2: Gpt2,
    pub gpio1: Port<1>,
    pub gpio2: Port<2>,
    pub gpio3: Port<3>,
    pub gpio4: Port<4>,
    pub usb: Instances<1>,
    pub dma: [Option<Channel>; 32],
    pub srtc: Disabled,
    pub snvs_lp_core: LpCore,
    pub ccm: CCM,
    pub ccm_analog: CCM_ANALOG,
    pub dcdc: DCDC,
    pub pins: Pins,
    pub lpi2c1: LPI2C1,
    pub lpi2c3: LPI2C3,
    pub lpspi1: LPSPI1,
    pub lpspi2: LPSPI2,
    pub lpspi3: LPSPI3,
    pub lpspi4: LPSPI4,
    pub lpuart6: LPUART6,
    pub lpuart4: LPUART4,
    pub lpuart2: LPUART2,
    pub lpuart3: LPUART3,
    pub lpuart8: LPUART8,
    pub lpuart1: LPUART1,
    pub lpuart5: LPUART5,
    pub lpuart7: LPUART7,
    pub flexpwm1: (Pwm<1>, Submodules<1>),
    pub flexpwm2: (Pwm<2>, Submodules<2>),
    pub flexpwm3: (Pwm<3>, Submodules<3>),
    pub flexpwm4: (Pwm<4>, Submodules<4>),
    pub flexio1: FLEXIO1,
    pub flexio2: FLEXIO2,
    pub flexio3: FLEXIO3,
    pub adc1: Adc<1>,
    pub adc2: Adc<2>,
    pub trng: Trng,
    pub tempmon: TempMon,
}

Resources constructed by the board.

The concrete Pins type depends on how this is constructed. See the various *Resources aliases for more information.

Fields (Non-exhaustive)

Non-exhaustive structs could have additional fields added in future. Therefore, non-exhaustive structs cannot be constructed in external crates using the traditional Struct { .. } syntax; cannot be matched against without a wildcard ..; and struct update syntax will not work.

pit: Channels

Periodic interrupt timer channels.

gpt1: Gpt1

General purpose timer 1.

gpt2: Gpt2

General purpose timer 2.

gpio1: Port<1>

GPIO1 port.

gpio2: Port<2>

GPIO2 port.

gpio3: Port<3>

GPIO3 port.

gpio4: Port<4>

GPIO4 port.

usb: Instances<1>

USB1 instances.

Use this to construct higher-level USB drivers, or to initialize the USB logger.

dma: [Option<Channel>; 32]

DMA channels.

srtc: Disabled

The secure real-time counter.

It’s initially disabled, and you may enable it in your firmware.

snvs_lp_core: LpCore

Core registers for the SNVS low-power domain.

Use this with the SRTC and other SNVS LP components.

ccm: CCM

Clock control module.

ccm_analog: CCM_ANALOG

Analog clock control module.

dcdc: DCDC

DCDC converter

pins: Pins

All available pins.

lpi2c1: LPI2C1

The register block for Lpi2c1.

lpi2c3: LPI2C3

The register block for Lpi2c3.

lpspi1: LPSPI1

The register blocks for Lpspi1.

lpspi2: LPSPI2

The register blocks for Lpspi2.

lpspi3: LPSPI3

The register blocks for Lpspi3.

lpspi4: LPSPI4

The register block for Lpspi4.

lpuart6: LPUART6

The register block for Lpuart6.

lpuart4: LPUART4

The register block for Lpuart4.

lpuart2: LPUART2

The register block for Lpuart2.

lpuart3: LPUART3

The register block for Lpuart3.

lpuart8: LPUART8

The register block for Lpuart8.

lpuart1: LPUART1

The register block for Lpuart1.

lpuart5: LPUART5

The register block for Lpuart5.

lpuart7: LPUART7

The register block for Lpuart7.

flexpwm1: (Pwm<1>, Submodules<1>)

FlexPWM1 components.

flexpwm2: (Pwm<2>, Submodules<2>)

FlexPWM2 components.

flexpwm3: (Pwm<3>, Submodules<3>)

FlexPWM3 components.

flexpwm4: (Pwm<4>, Submodules<4>)

FlexPWM4 components.

flexio1: FLEXIO1

The FlexIO1 register block.

flexio2: FLEXIO2

The FlexIO2 register block.

flexio3: FLEXIO3

The FlexIO3 register block.

adc1: Adc<1>

The register block for ADC1.

ADC drivers constructed by board use a pre-configured clock and divisor. To change this configuration, call release() to acquire the register block, then re-construct the driver.

adc2: Adc<2>

The register block for ADC2.

trng: Trng

True random number generator.

tempmon: TempMon

Temperature monitor of the core.